The Memory Map

Supported Designs

Here you can find the complete memory MAP for the supported designs. This will include the TDC registers as well as the carrier registers and any other component used in an FMC-TDC-1NS-5CH design.

Table of Contents

TDC memory map

Following the memory map for the part of the TDC design that drives the FMC-TDC-1NS-5CH modules.

fmc_tdc_mezzanine_mmap

fmc_tdc_mezzanine_mmap

FMC-TDC-1NS-5CH mezzanine memory map

1. Memory map summary

HW address Type Name HDL prefix C prefix
0x1000-0x1fff SUBMAP one-wire one-wire one-wire
0x2000-0x2fff SUBMAP core core core
0x3000-0x3fff SUBMAP eic eic eic
0x4000-0x4fff SUBMAP i2c i2c i2c
0x5000-0x5fff SUBMAP mem mem mem
0x6000-0x6fff SUBMAP mem-dma mem-dma mem-dma
0x7000-0x7fff SUBMAP mem-dma-eic mem-dma-eic mem-dma-eic

2. Register description

One wire

tdc_onewire_wb

tdc_onewire_wb

TDC Onewire Master

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Status Register
3.2. Board Temperature
3.3. Board Unique ID (MSW)
3.4. Board Unique ID (LSW)

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x0 REG Status Register tdc_ow_csr CSR
0x1 REG Board Temperature tdc_ow_temp TEMP
0x2 REG Board Unique ID (MSW) tdc_ow_id_h ID_H
0x3 REG Board Unique ID (LSW) tdc_ow_id_l ID_L

2. HDL symbol

⇒ wb_adr_i[1:0] Status Register:
⇒ wb_dat_i[31:0] tdc_ow_csr_valid_o →
⇐ wb_dat_o[31:0] tdc_ow_csr_valid_i ←
→ wb_cyc_i tdc_ow_csr_valid_load_o →
⇒ wb_sel_i[3:0]  
→ wb_stb_i Board Temperature:
→ wb_we_i tdc_ow_temp_i[15:0] ⇐
← wb_ack_o  
← wb_err_o Board Unique ID (MSW):
← wb_rty_o tdc_ow_id_h_i[31:0] ⇐
← wb_stall_o  
Board Unique ID (LSW):
tdc_ow_id_l_i[31:0] ⇐

3. Register description

3.1. Status Register

HW prefix: tdc_ow_csr
HW address: 0x0
C prefix: CSR
C offset: 0x0
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - VALID
  • VALID [read/write]: Temperature and ID valid
    read 1: the values in the TEMP, ID_H, ID_L registers contain a valid readout from the DS18xx chip

3.2. Board Temperature

HW prefix: tdc_ow_temp
HW address: 0x1
C prefix: TEMP
C offset: 0x4
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TEMP[15:8]
7 6 5 4 3 2 1 0
TEMP[7:0]
  • TEMP [read-only]: Temperature

3.3. Board Unique ID (MSW)

HW prefix: tdc_ow_id_h
HW address: 0x2
C prefix: ID_H
C offset: 0x8
31 30 29 28 27 26 25 24
ID_H[31:24]
23 22 21 20 19 18 17 16
ID_H[23:16]
15 14 13 12 11 10 9 8
ID_H[15:8]
7 6 5 4 3 2 1 0
ID_H[7:0]
  • ID_H [read-only]: Unique ID (32 highest bits)

3.4. Board Unique ID (LSW)

HW prefix: tdc_ow_id_l
HW address: 0x3
C prefix: ID_L
C offset: 0xc
31 30 29 28 27 26 25 24
ID_L[31:24]
23 22 21 20 19 18 17 16
ID_L[23:16]
15 14 13 12 11 10 9 8
ID_L[15:8]
7 6 5 4 3 2 1 0
ID_L[7:0]
  • ID_L [read-only]: Unique ID (32 lowest bits)

Core

EIC

tdc_eic

tdc_eic

TDC EIC

FMC TDC embedded interrrupt controller.

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Interrupt disable register
3.2. Interrupt enable register
3.3. Interrupt mask register
3.4. Interrupt status register
5. Interrupts
5.1. FMC TDC timestamps interrupt (FIFO1)
5.2. FMC TDC timestamps interrupt (FIFO2)
5.3. FMC TDC timestamps interrupt (FIFO3)
5.4. FMC TDC timestamps interrupt (FIFO4)
5.5. FMC TDC timestamps interrupt (FIFO5)
5.6. FMC TDC timestamps interrupt (DMA1)
5.7. FMC TDC timestamps interrupt (DMA2)
5.8. FMC TDC timestamps interrupt (DMA3)
5.9. FMC TDC timestamps interrupt (DMA4)
5.10. FMC TDC timestamps interrupt (DMA5)

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x8 REG Interrupt disable register tdc_eic_eic_idr EIC_IDR
0x9 REG Interrupt enable register tdc_eic_eic_ier EIC_IER
0xa REG Interrupt mask register tdc_eic_eic_imr EIC_IMR
0xb REG Interrupt status register tdc_eic_eic_isr EIC_ISR

2. HDL symbol

⇒ wb_adr_i[3:0] FMC TDC timestamps interrupt (FIFO1):
⇒ wb_dat_i[31:0] irq_tdc_fifo1_i ←
⇐ wb_dat_o[31:0]  
→ wb_cyc_i FMC TDC timestamps interrupt (FIFO2):
⇒ wb_sel_i[3:0] irq_tdc_fifo2_i ←
→ wb_stb_i  
→ wb_we_i FMC TDC timestamps interrupt (FIFO3):
← wb_ack_o irq_tdc_fifo3_i ←
← wb_err_o  
← wb_rty_o FMC TDC timestamps interrupt (FIFO4):
← wb_stall_o irq_tdc_fifo4_i ←
← wb_int_o  
FMC TDC timestamps interrupt (FIFO5):
irq_tdc_fifo5_i ←
 
FMC TDC timestamps interrupt (DMA1):
irq_tdc_dma1_i ←
 
FMC TDC timestamps interrupt (DMA2):
irq_tdc_dma2_i ←
 
FMC TDC timestamps interrupt (DMA3):
irq_tdc_dma3_i ←
 
FMC TDC timestamps interrupt (DMA4):
irq_tdc_dma4_i ←
 
FMC TDC timestamps interrupt (DMA5):
irq_tdc_dma5_i ←

3. Register description

3.1. Interrupt disable register

HW prefix: tdc_eic_eic_idr
HW address: 0x8
C prefix: EIC_IDR
C offset: 0x20

Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - TDC_DMA5 TDC_DMA4
7 6 5 4 3 2 1 0
TDC_DMA3 TDC_DMA2 TDC_DMA1 TDC_FIFO5 TDC_FIFO4 TDC_FIFO3 TDC_FIFO2 TDC_FIFO1
  • TDC_FIFO1 [write-only]: FMC TDC timestamps interrupt (FIFO1)
    write 1: disable interrupt 'FMC TDC timestamps interrupt (FIFO1)'
    write 0: no effect
  • TDC_FIFO2 [write-only]: FMC TDC timestamps interrupt (FIFO2)
    write 1: disable interrupt 'FMC TDC timestamps interrupt (FIFO2)'
    write 0: no effect
  • TDC_FIFO3 [write-only]: FMC TDC timestamps interrupt (FIFO3)
    write 1: disable interrupt 'FMC TDC timestamps interrupt (FIFO3)'
    write 0: no effect
  • TDC_FIFO4 [write-only]: FMC TDC timestamps interrupt (FIFO4)
    write 1: disable interrupt 'FMC TDC timestamps interrupt (FIFO4)'
    write 0: no effect
  • TDC_FIFO5 [write-only]: FMC TDC timestamps interrupt (FIFO5)
    write 1: disable interrupt 'FMC TDC timestamps interrupt (FIFO5)'
    write 0: no effect
  • TDC_DMA1 [write-only]: FMC TDC timestamps interrupt (DMA1)
    write 1: disable interrupt 'FMC TDC timestamps interrupt (DMA1)'
    write 0: no effect
  • TDC_DMA2 [write-only]: FMC TDC timestamps interrupt (DMA2)
    write 1: disable interrupt 'FMC TDC timestamps interrupt (DMA2)'
    write 0: no effect
  • TDC_DMA3 [write-only]: FMC TDC timestamps interrupt (DMA3)
    write 1: disable interrupt 'FMC TDC timestamps interrupt (DMA3)'
    write 0: no effect
  • TDC_DMA4 [write-only]: FMC TDC timestamps interrupt (DMA4)
    write 1: disable interrupt 'FMC TDC timestamps interrupt (DMA4)'
    write 0: no effect
  • TDC_DMA5 [write-only]: FMC TDC timestamps interrupt (DMA5)
    write 1: disable interrupt 'FMC TDC timestamps interrupt (DMA5)'
    write 0: no effect

3.2. Interrupt enable register

HW prefix: tdc_eic_eic_ier
HW address: 0x9
C prefix: EIC_IER
C offset: 0x24

Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - TDC_DMA5 TDC_DMA4
7 6 5 4 3 2 1 0
TDC_DMA3 TDC_DMA2 TDC_DMA1 TDC_FIFO5 TDC_FIFO4 TDC_FIFO3 TDC_FIFO2 TDC_FIFO1
  • TDC_FIFO1 [write-only]: FMC TDC timestamps interrupt (FIFO1)
    write 1: enable interrupt 'FMC TDC timestamps interrupt (FIFO1)'
    write 0: no effect
  • TDC_FIFO2 [write-only]: FMC TDC timestamps interrupt (FIFO2)
    write 1: enable interrupt 'FMC TDC timestamps interrupt (FIFO2)'
    write 0: no effect
  • TDC_FIFO3 [write-only]: FMC TDC timestamps interrupt (FIFO3)
    write 1: enable interrupt 'FMC TDC timestamps interrupt (FIFO3)'
    write 0: no effect
  • TDC_FIFO4 [write-only]: FMC TDC timestamps interrupt (FIFO4)
    write 1: enable interrupt 'FMC TDC timestamps interrupt (FIFO4)'
    write 0: no effect
  • TDC_FIFO5 [write-only]: FMC TDC timestamps interrupt (FIFO5)
    write 1: enable interrupt 'FMC TDC timestamps interrupt (FIFO5)'
    write 0: no effect
  • TDC_DMA1 [write-only]: FMC TDC timestamps interrupt (DMA1)
    write 1: enable interrupt 'FMC TDC timestamps interrupt (DMA1)'
    write 0: no effect
  • TDC_DMA2 [write-only]: FMC TDC timestamps interrupt (DMA2)
    write 1: enable interrupt 'FMC TDC timestamps interrupt (DMA2)'
    write 0: no effect
  • TDC_DMA3 [write-only]: FMC TDC timestamps interrupt (DMA3)
    write 1: enable interrupt 'FMC TDC timestamps interrupt (DMA3)'
    write 0: no effect
  • TDC_DMA4 [write-only]: FMC TDC timestamps interrupt (DMA4)
    write 1: enable interrupt 'FMC TDC timestamps interrupt (DMA4)'
    write 0: no effect
  • TDC_DMA5 [write-only]: FMC TDC timestamps interrupt (DMA5)
    write 1: enable interrupt 'FMC TDC timestamps interrupt (DMA5)'
    write 0: no effect

3.3. Interrupt mask register

HW prefix: tdc_eic_eic_imr
HW address: 0xa
C prefix: EIC_IMR
C offset: 0x28

Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - TDC_DMA5 TDC_DMA4
7 6 5 4 3 2 1 0
TDC_DMA3 TDC_DMA2 TDC_DMA1 TDC_FIFO5 TDC_FIFO4 TDC_FIFO3 TDC_FIFO2 TDC_FIFO1
  • TDC_FIFO1 [read-only]: FMC TDC timestamps interrupt (FIFO1)
    read 1: interrupt 'FMC TDC timestamps interrupt (FIFO1)' is enabled
    read 0: interrupt 'FMC TDC timestamps interrupt (FIFO1)' is disabled
  • TDC_FIFO2 [read-only]: FMC TDC timestamps interrupt (FIFO2)
    read 1: interrupt 'FMC TDC timestamps interrupt (FIFO2)' is enabled
    read 0: interrupt 'FMC TDC timestamps interrupt (FIFO2)' is disabled
  • TDC_FIFO3 [read-only]: FMC TDC timestamps interrupt (FIFO3)
    read 1: interrupt 'FMC TDC timestamps interrupt (FIFO3)' is enabled
    read 0: interrupt 'FMC TDC timestamps interrupt (FIFO3)' is disabled
  • TDC_FIFO4 [read-only]: FMC TDC timestamps interrupt (FIFO4)
    read 1: interrupt 'FMC TDC timestamps interrupt (FIFO4)' is enabled
    read 0: interrupt 'FMC TDC timestamps interrupt (FIFO4)' is disabled
  • TDC_FIFO5 [read-only]: FMC TDC timestamps interrupt (FIFO5)
    read 1: interrupt 'FMC TDC timestamps interrupt (FIFO5)' is enabled
    read 0: interrupt 'FMC TDC timestamps interrupt (FIFO5)' is disabled
  • TDC_DMA1 [read-only]: FMC TDC timestamps interrupt (DMA1)
    read 1: interrupt 'FMC TDC timestamps interrupt (DMA1)' is enabled
    read 0: interrupt 'FMC TDC timestamps interrupt (DMA1)' is disabled
  • TDC_DMA2 [read-only]: FMC TDC timestamps interrupt (DMA2)
    read 1: interrupt 'FMC TDC timestamps interrupt (DMA2)' is enabled
    read 0: interrupt 'FMC TDC timestamps interrupt (DMA2)' is disabled
  • TDC_DMA3 [read-only]: FMC TDC timestamps interrupt (DMA3)
    read 1: interrupt 'FMC TDC timestamps interrupt (DMA3)' is enabled
    read 0: interrupt 'FMC TDC timestamps interrupt (DMA3)' is disabled
  • TDC_DMA4 [read-only]: FMC TDC timestamps interrupt (DMA4)
    read 1: interrupt 'FMC TDC timestamps interrupt (DMA4)' is enabled
    read 0: interrupt 'FMC TDC timestamps interrupt (DMA4)' is disabled
  • TDC_DMA5 [read-only]: FMC TDC timestamps interrupt (DMA5)
    read 1: interrupt 'FMC TDC timestamps interrupt (DMA5)' is enabled
    read 0: interrupt 'FMC TDC timestamps interrupt (DMA5)' is disabled

3.4. Interrupt status register

HW prefix: tdc_eic_eic_isr
HW address: 0xb
C prefix: EIC_ISR
C offset: 0x2c

Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - TDC_DMA5 TDC_DMA4
7 6 5 4 3 2 1 0
TDC_DMA3 TDC_DMA2 TDC_DMA1 TDC_FIFO5 TDC_FIFO4 TDC_FIFO3 TDC_FIFO2 TDC_FIFO1
  • TDC_FIFO1 [read/write]: FMC TDC timestamps interrupt (FIFO1)
    read 1: interrupt 'FMC TDC timestamps interrupt (FIFO1)' is pending
    read 0: interrupt not pending
    write 1: clear interrupt 'FMC TDC timestamps interrupt (FIFO1)'
    write 0: no effect
  • TDC_FIFO2 [read/write]: FMC TDC timestamps interrupt (FIFO2)
    read 1: interrupt 'FMC TDC timestamps interrupt (FIFO2)' is pending
    read 0: interrupt not pending
    write 1: clear interrupt 'FMC TDC timestamps interrupt (FIFO2)'
    write 0: no effect
  • TDC_FIFO3 [read/write]: FMC TDC timestamps interrupt (FIFO3)
    read 1: interrupt 'FMC TDC timestamps interrupt (FIFO3)' is pending
    read 0: interrupt not pending
    write 1: clear interrupt 'FMC TDC timestamps interrupt (FIFO3)'
    write 0: no effect
  • TDC_FIFO4 [read/write]: FMC TDC timestamps interrupt (FIFO4)
    read 1: interrupt 'FMC TDC timestamps interrupt (FIFO4)' is pending
    read 0: interrupt not pending
    write 1: clear interrupt 'FMC TDC timestamps interrupt (FIFO4)'
    write 0: no effect
  • TDC_FIFO5 [read/write]: FMC TDC timestamps interrupt (FIFO5)
    read 1: interrupt 'FMC TDC timestamps interrupt (FIFO5)' is pending
    read 0: interrupt not pending
    write 1: clear interrupt 'FMC TDC timestamps interrupt (FIFO5)'
    write 0: no effect
  • TDC_DMA1 [read/write]: FMC TDC timestamps interrupt (DMA1)
    read 1: interrupt 'FMC TDC timestamps interrupt (DMA1)' is pending
    read 0: interrupt not pending
    write 1: clear interrupt 'FMC TDC timestamps interrupt (DMA1)'
    write 0: no effect
  • TDC_DMA2 [read/write]: FMC TDC timestamps interrupt (DMA2)
    read 1: interrupt 'FMC TDC timestamps interrupt (DMA2)' is pending
    read 0: interrupt not pending
    write 1: clear interrupt 'FMC TDC timestamps interrupt (DMA2)'
    write 0: no effect
  • TDC_DMA3 [read/write]: FMC TDC timestamps interrupt (DMA3)
    read 1: interrupt 'FMC TDC timestamps interrupt (DMA3)' is pending
    read 0: interrupt not pending
    write 1: clear interrupt 'FMC TDC timestamps interrupt (DMA3)'
    write 0: no effect
  • TDC_DMA4 [read/write]: FMC TDC timestamps interrupt (DMA4)
    read 1: interrupt 'FMC TDC timestamps interrupt (DMA4)' is pending
    read 0: interrupt not pending
    write 1: clear interrupt 'FMC TDC timestamps interrupt (DMA4)'
    write 0: no effect
  • TDC_DMA5 [read/write]: FMC TDC timestamps interrupt (DMA5)
    read 1: interrupt 'FMC TDC timestamps interrupt (DMA5)' is pending
    read 0: interrupt not pending
    write 1: clear interrupt 'FMC TDC timestamps interrupt (DMA5)'
    write 0: no effect

5. Interrupts

5.1. FMC TDC timestamps interrupt (FIFO1)

HW prefix: tdc_eic_tdc_fifo1
C prefix: TDC_FIFO1
Trigger: high level

FMC TDC FIFO1 not empty.

5.2. FMC TDC timestamps interrupt (FIFO2)

HW prefix: tdc_eic_tdc_fifo2
C prefix: TDC_FIFO2
Trigger: high level

FMC TDC FIFO1 not empty.

5.3. FMC TDC timestamps interrupt (FIFO3)

HW prefix: tdc_eic_tdc_fifo3
C prefix: TDC_FIFO3
Trigger: high level

FMC TDC FIFO3 not empty.

5.4. FMC TDC timestamps interrupt (FIFO4)

HW prefix: tdc_eic_tdc_fifo4
C prefix: TDC_FIFO4
Trigger: high level

FMC TDC FIFO4 not empty.

5.5. FMC TDC timestamps interrupt (FIFO5)

HW prefix: tdc_eic_tdc_fifo5
C prefix: TDC_FIFO5
Trigger: high level

FMC TDC FIFO5 not empty.

5.6. FMC TDC timestamps interrupt (DMA1)

HW prefix: tdc_eic_tdc_dma1
C prefix: TDC_DMA1
Trigger: high level

FMC TDC DMA1 acquisition ready.

5.7. FMC TDC timestamps interrupt (DMA2)

HW prefix: tdc_eic_tdc_dma2
C prefix: TDC_DMA2
Trigger: high level

FMC TDC DMA1 acquisition ready.

5.8. FMC TDC timestamps interrupt (DMA3)

HW prefix: tdc_eic_tdc_dma3
C prefix: TDC_DMA3
Trigger: high level

FMC TDC DMA3 acquisition ready.

5.9. FMC TDC timestamps interrupt (DMA4)

HW prefix: tdc_eic_tdc_dma4
C prefix: TDC_DMA4
Trigger: high level

FMC TDC DMA4 acquisition ready.

5.10. FMC TDC timestamps interrupt (DMA5)

HW prefix: tdc_eic_tdc_dma5
C prefix: TDC_DMA5
Trigger: high level

FMC TDC DMA5 acquisition ready.

I2C

Not used.

Mem

timestamp_fifo_wb

timestamp_fifo_wb

Timestamp FIFO

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Delta Timestamp Word 1
3.2. Delta Timestamp Word 2
3.3. Delta Timestamp Word 3
3.4. Channel Offset Word 1
3.5. Channel Offset Word 2
3.6. Channel Offset Word 3
3.7. Control/Status
3.8. FIFO 'Timestamp FIFO' data output register 0
3.9. FIFO 'Timestamp FIFO' data output register 1
3.10. FIFO 'Timestamp FIFO' data output register 2
3.11. FIFO 'Timestamp FIFO' data output register 3
3.12. FIFO 'Timestamp FIFO' control/status register

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x0 REG Delta Timestamp Word 1 tsf_delta1 DELTA1
0x1 REG Delta Timestamp Word 2 tsf_delta2 DELTA2
0x2 REG Delta Timestamp Word 3 tsf_delta3 DELTA3
0x3 REG Channel Offset Word 1 tsf_offset1 OFFSET1
0x4 REG Channel Offset Word 2 tsf_offset2 OFFSET2
0x5 REG Channel Offset Word 3 tsf_offset3 OFFSET3
0x6 REG Control/Status tsf_csr CSR
0x7 FIFOREG FIFO 'Timestamp FIFO' data output register 0 tsf_fifo_r0 FIFO_R0
0x8 FIFOREG FIFO 'Timestamp FIFO' data output register 1 tsf_fifo_r1 FIFO_R1
0x9 FIFOREG FIFO 'Timestamp FIFO' data output register 2 tsf_fifo_r2 FIFO_R2
0xa FIFOREG FIFO 'Timestamp FIFO' data output register 3 tsf_fifo_r3 FIFO_R3
0xb REG FIFO 'Timestamp FIFO' control/status register tsf_fifo_csr FIFO_CSR

2. HDL symbol

⇒ wb_adr_i[3:0] Timestamp FIFO:
⇒ wb_dat_i[31:0] tsf_fifo_wr_req_i ←
⇐ wb_dat_o[31:0] tsf_fifo_wr_full_o →
→ wb_cyc_i tsf_fifo_wr_empty_o →
⇒ wb_sel_i[3:0] tsf_fifo_wr_usedw_o[5:0] ⇒
→ wb_stb_i tsf_fifo_ts0_i[31:0] ⇐
→ wb_we_i tsf_fifo_ts1_i[31:0] ⇐
← wb_ack_o tsf_fifo_ts2_i[31:0] ⇐
← wb_err_o tsf_fifo_ts3_i[31:0] ⇐
← wb_rty_o  
← wb_stall_o Delta Timestamp Word 1:
tsf_delta1_i[31:0] ⇐
 
Delta Timestamp Word 2:
tsf_delta2_i[31:0] ⇐
 
Delta Timestamp Word 3:
tsf_delta3_i[31:0] ⇐
 
Channel Offset Word 1:
tsf_offset1_o[31:0] ⇒
 
Channel Offset Word 2:
tsf_offset2_o[31:0] ⇒
 
Channel Offset Word 3:
tsf_offset3_o[31:0] ⇒
 
Control/Status:
tsf_csr_delta_ready_i ←
tsf_csr_delta_read_o →
tsf_csr_rst_seq_o →
tsf_csr_delta_ref_o[2:0] ⇒
tsf_csr_raw_mode_o →
 
FIFO 'Timestamp FIFO' data output register 0:
 
FIFO 'Timestamp FIFO' data output register 1:
 
FIFO 'Timestamp FIFO' data output register 2:
 
FIFO 'Timestamp FIFO' data output register 3:

3. Register description

3.1. Delta Timestamp Word 1

HW prefix: tsf_delta1
HW address: 0x0
C prefix: DELTA1
C offset: 0x0
31 30 29 28 27 26 25 24
DELTA1[31:24]
23 22 21 20 19 18 17 16
DELTA1[23:16]
15 14 13 12 11 10 9 8
DELTA1[15:8]
7 6 5 4 3 2 1 0
DELTA1[7:0]
  • DELTA1 [read-only]: Delta Timestamp Word 1 (TAI cycles, signed)

3.2. Delta Timestamp Word 2

HW prefix: tsf_delta2
HW address: 0x1
C prefix: DELTA2
C offset: 0x4
31 30 29 28 27 26 25 24
DELTA2[31:24]
23 22 21 20 19 18 17 16
DELTA2[23:16]
15 14 13 12 11 10 9 8
DELTA2[15:8]
7 6 5 4 3 2 1 0
DELTA2[7:0]
  • DELTA2 [read-only]: Delta Timestamp Word 2 (8ns ticks, unsigned)

3.3. Delta Timestamp Word 3

HW prefix: tsf_delta3
HW address: 0x2
C prefix: DELTA3
C offset: 0x8
31 30 29 28 27 26 25 24
DELTA3[31:24]
23 22 21 20 19 18 17 16
DELTA3[23:16]
15 14 13 12 11 10 9 8
DELTA3[15:8]
7 6 5 4 3 2 1 0
DELTA3[7:0]
  • DELTA3 [read-only]: Delta Timestamp Word 3 (fractional part, unsigned)

3.4. Channel Offset Word 1

HW prefix: tsf_offset1
HW address: 0x3
C prefix: OFFSET1
C offset: 0xc
31 30 29 28 27 26 25 24
OFFSET1[31:24]
23 22 21 20 19 18 17 16
OFFSET1[23:16]
15 14 13 12 11 10 9 8
OFFSET1[15:8]
7 6 5 4 3 2 1 0
OFFSET1[7:0]
  • OFFSET1 [read/write]: Channel Offset Word 1 (TAI cycles, signed)

3.5. Channel Offset Word 2

HW prefix: tsf_offset2
HW address: 0x4
C prefix: OFFSET2
C offset: 0x10
31 30 29 28 27 26 25 24
OFFSET2[31:24]
23 22 21 20 19 18 17 16
OFFSET2[23:16]
15 14 13 12 11 10 9 8
OFFSET2[15:8]
7 6 5 4 3 2 1 0
OFFSET2[7:0]
  • OFFSET2 [read/write]: Channel Offset Word 2 (8ns ticks, unsigned)

3.6. Channel Offset Word 3

HW prefix: tsf_offset3
HW address: 0x5
C prefix: OFFSET3
C offset: 0x14
31 30 29 28 27 26 25 24
OFFSET3[31:24]
23 22 21 20 19 18 17 16
OFFSET3[23:16]
15 14 13 12 11 10 9 8
OFFSET3[15:8]
7 6 5 4 3 2 1 0
OFFSET3[7:0]
  • OFFSET3 [read/write]: Channel Offset Word 3 (fractional part, unsigned)

3.7. Control/Status

HW prefix: tsf_csr
HW address: 0x6
C prefix: CSR
C offset: 0x18
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- RAW_MODE DELTA_REF[2:0] RST_SEQ DELTA_READ DELTA_READY
  • DELTA_READY [read-only]: Delta Timestamp Ready
  • DELTA_READ [write-only]: Read Delta Timestamp
  • RST_SEQ [write-only]: Reset Sequence Counter
  • DELTA_REF [read/write]: Delta Timestamp Reference Channel
    Channel (0-4) to take as the reference for the delta timestamps
  • RAW_MODE [read/write]: Raw readout mode
    1: enables readout of raw timestamps

3.8. FIFO 'Timestamp FIFO' data output register 0

HW prefix: tsf_fifo_r0
HW address: 0x7
C prefix: FIFO_R0
C offset: 0x1c
31 30 29 28 27 26 25 24
TS0[31:24]
23 22 21 20 19 18 17 16
TS0[23:16]
15 14 13 12 11 10 9 8
TS0[15:8]
7 6 5 4 3 2 1 0
TS0[7:0]
  • TS0 [read-only]: The timestamp (word 0)

3.9. FIFO 'Timestamp FIFO' data output register 1

HW prefix: tsf_fifo_r1
HW address: 0x8
C prefix: FIFO_R1
C offset: 0x20
31 30 29 28 27 26 25 24
TS1[31:24]
23 22 21 20 19 18 17 16
TS1[23:16]
15 14 13 12 11 10 9 8
TS1[15:8]
7 6 5 4 3 2 1 0
TS1[7:0]
  • TS1 [read-only]: The timestamp (word 1)

3.10. FIFO 'Timestamp FIFO' data output register 2

HW prefix: tsf_fifo_r2
HW address: 0x9
C prefix: FIFO_R2
C offset: 0x24
31 30 29 28 27 26 25 24
TS2[31:24]
23 22 21 20 19 18 17 16
TS2[23:16]
15 14 13 12 11 10 9 8
TS2[15:8]
7 6 5 4 3 2 1 0
TS2[7:0]
  • TS2 [read-only]: The timestamp (word 2)

3.11. FIFO 'Timestamp FIFO' data output register 3

HW prefix: tsf_fifo_r3
HW address: 0xa
C prefix: FIFO_R3
C offset: 0x28
31 30 29 28 27 26 25 24
TS3[31:24]
23 22 21 20 19 18 17 16
TS3[23:16]
15 14 13 12 11 10 9 8
TS3[15:8]
7 6 5 4 3 2 1 0
TS3[7:0]
  • TS3 [read-only]: The timestamp (word 3)

3.12. FIFO 'Timestamp FIFO' control/status register

HW prefix: tsf_fifo_csr
HW address: 0xb
C prefix: FIFO_CSR
C offset: 0x2c
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - CLEAR_BUS EMPTY FULL
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - USEDW[5:0]
  • FULL [read-only]: FIFO full flag
    1: FIFO 'Timestamp FIFO' is full
    0: FIFO is not full
  • EMPTY [read-only]: FIFO empty flag
    1: FIFO 'Timestamp FIFO' is empty
    0: FIFO is not empty
  • CLEAR_BUS [write-only]: FIFO clear
    write 1: clears FIFO 'Timestamp FIFO
    write 0: no effect
  • USEDW [read-only]: FIFO counter
    Number of data records currently being stored in FIFO 'Timestamp FIFO'

Mem DMA

tdc_buffer_control_wb

tdc_buffer_control_wb

TDC DMA Buffer Control Registers

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Control/Status register
3.2. Current buffer base address register
3.3. Current buffer base count register
3.4. Current buffer base size/valid flag register
3.5. Next buffer base address register
3.6. Next buffer base size/valid flag register

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x0 REG Control/Status register tdc_buf_csr CSR
0x1 REG Current buffer base address register tdc_buf_cur_base CUR_BASE
0x2 REG Current buffer base count register tdc_buf_cur_count CUR_COUNT
0x3 REG Current buffer base size/valid flag register tdc_buf_cur_size CUR_SIZE
0x4 REG Next buffer base address register tdc_buf_next_base NEXT_BASE
0x5 REG Next buffer base size/valid flag register tdc_buf_next_size NEXT_SIZE

2. HDL symbol

⇒ wb_adr_i[2:0] Control/Status register:
⇒ wb_dat_i[31:0] tdc_buf_csr_enable_o →
⇐ wb_dat_o[31:0] tdc_buf_csr_irq_timeout_o[9:0] ⇒
→ wb_cyc_i tdc_buf_csr_burst_size_o[9:0] ⇒
⇒ wb_sel_i[3:0] tdc_buf_csr_switch_buffers_o →
→ wb_stb_i tdc_buf_csr_done_o →
→ wb_we_i tdc_buf_csr_done_i ←
← wb_ack_o tdc_buf_csr_done_load_o →
← wb_err_o tdc_buf_csr_overflow_o →
← wb_rty_o tdc_buf_csr_overflow_i ←
← wb_stall_o tdc_buf_csr_overflow_load_o →
 
Current buffer base address register:
tdc_buf_cur_base_o[31:0] ⇒
tdc_buf_cur_base_i[31:0] ⇐
tdc_buf_cur_base_load_o →
 
Current buffer base count register:
tdc_buf_cur_count_i[31:0] ⇐
 
Current buffer base size/valid flag register:
tdc_buf_cur_size_size_o[29:0] ⇒
tdc_buf_cur_size_size_i[29:0] ⇐
tdc_buf_cur_size_size_load_o →
tdc_buf_cur_size_valid_o →
tdc_buf_cur_size_valid_i ←
tdc_buf_cur_size_valid_load_o →
 
Next buffer base address register:
tdc_buf_next_base_o[31:0] ⇒
tdc_buf_next_base_i[31:0] ⇐
tdc_buf_next_base_load_o →
 
Next buffer base size/valid flag register:
tdc_buf_next_size_size_o[29:0] ⇒
tdc_buf_next_size_size_i[29:0] ⇐
tdc_buf_next_size_size_load_o →
tdc_buf_next_size_valid_o →
tdc_buf_next_size_valid_i ←
tdc_buf_next_size_valid_load_o →

3. Register description

3.1. Control/Status register

HW prefix: tdc_buf_csr
HW address: 0x0
C prefix: CSR
C offset: 0x0
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
OVERFLOW DONE SWITCH_BUFFERS BURST_SIZE[9:5]
15 14 13 12 11 10 9 8
BURST_SIZE[4:0] IRQ_TIMEOUT[9:7]
7 6 5 4 3 2 1 0
IRQ_TIMEOUT[6:0] ENABLE
  • ENABLE [read/write]: Enable acquisition
    1: timestamps of the given channel will be sequentially written to the current buffer, provided it's valid (CUR_SIZE.VALID=1)
    0: acquisition off
  • IRQ_TIMEOUT [read/write]: IRQ Timeout (ms)
    Interrupt coalescing timeout in milliseconds. Pick a high enough value to avoid too frequent interrupts and a low enough one to prevent buffer contention. 10 ms should be OK for most of the cases
  • BURST_SIZE [read/write]: Burst size (timestamps)
    Number of timestamps in a single burst to the DDR memory. Default = 16
  • SWITCH_BUFFERS [write-only]: Switch buffers
    write 1: atomically switches the acquisition buffer from the current one (base/size in CUR_BASE/CUR_SIZE) to the next one (described in NEXT_BASE/NEXT_SIZE registers)
    write 0: no action
  • DONE [read/write]: Burst complete
    read 1: the current buffer has been fully committed to the DDR memory after writing 1 to SWITCH_BUFFERS field.
    read 0: still some transfers pending
  • OVERFLOW [read/write]: DMA overflow
    read 1: both the current and the next buffer have been filled with timestamps. Dropping all new incoming TS.

3.2. Current buffer base address register

HW prefix: tdc_buf_cur_base
HW address: 0x1
C prefix: CUR_BASE
C offset: 0x4
31 30 29 28 27 26 25 24
CUR_BASE[31:24]
23 22 21 20 19 18 17 16
CUR_BASE[23:16]
15 14 13 12 11 10 9 8
CUR_BASE[15:8]
7 6 5 4 3 2 1 0
CUR_BASE[7:0]
  • CUR_BASE [read/write]: Base address
    Base address of the current buffer (in bytes) relative to the DDR3 chip (0 = first word in the memory)

3.3. Current buffer base count register

HW prefix: tdc_buf_cur_count
HW address: 0x2
C prefix: CUR_COUNT
C offset: 0x8
31 30 29 28 27 26 25 24
CUR_COUNT[31:24]
23 22 21 20 19 18 17 16
CUR_COUNT[23:16]
15 14 13 12 11 10 9 8
CUR_COUNT[15:8]
7 6 5 4 3 2 1 0
CUR_COUNT[7:0]
  • CUR_COUNT [read-only]: Number of data samples
    Number of data samples in the buffer (1 sample = 1 timestamp)

3.4. Current buffer base size/valid flag register

HW prefix: tdc_buf_cur_size
HW address: 0x3
C prefix: CUR_SIZE
C offset: 0xc
31 30 29 28 27 26 25 24
- VALID SIZE[29:24]
23 22 21 20 19 18 17 16
SIZE[23:16]
15 14 13 12 11 10 9 8
SIZE[15:8]
7 6 5 4 3 2 1 0
SIZE[7:0]
  • SIZE [read/write]: Size
    Number of data samples the buffer can hold (1 sample = 1 timestamp)
  • VALID [read/write]: Valid flag
    write 1: indicate that this buffer is ready for acquisition and correctly configured

3.5. Next buffer base address register

HW prefix: tdc_buf_next_base
HW address: 0x4
C prefix: NEXT_BASE
C offset: 0x10
31 30 29 28 27 26 25 24
NEXT_BASE[31:24]
23 22 21 20 19 18 17 16
NEXT_BASE[23:16]
15 14 13 12 11 10 9 8
NEXT_BASE[15:8]
7 6 5 4 3 2 1 0
NEXT_BASE[7:0]
  • NEXT_BASE [read/write]: Base address

3.6. Next buffer base size/valid flag register

HW prefix: tdc_buf_next_size
HW address: 0x5
C prefix: NEXT_SIZE
C offset: 0x14
31 30 29 28 27 26 25 24
- VALID SIZE[29:24]
23 22 21 20 19 18 17 16
SIZE[23:16]
15 14 13 12 11 10 9 8
SIZE[15:8]
7 6 5 4 3 2 1 0
SIZE[7:0]
  • SIZE [read/write]: Size (in transfers)
  • VALID [read/write]: Valid flag

Mem DMA EIC

dma_eic

dma_eic

GN4124 DMA enhanced interrupt controller

Enhanced interrrupt controller for GN4124 DMA.

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Interrupt disable register
3.2. Interrupt enable register
3.3. Interrupt mask register
3.4. Interrupt status register
5. Interrupts
5.1. DMA done interrupt
5.2. DMA error interrupt

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x8 REG Interrupt disable register dma_eic_eic_idr EIC_IDR
0x9 REG Interrupt enable register dma_eic_eic_ier EIC_IER
0xa REG Interrupt mask register dma_eic_eic_imr EIC_IMR
0xb REG Interrupt status register dma_eic_eic_isr EIC_ISR

2. HDL symbol

⇒ wb_adr_i[3:0] DMA done interrupt:
⇒ wb_dat_i[31:0] irq_dma_done_i ←
⇐ wb_dat_o[31:0]  
→ wb_cyc_i DMA error interrupt:
⇒ wb_sel_i[3:0] irq_dma_error_i ←
→ wb_stb_i
→ wb_we_i
← wb_ack_o
← wb_err_o
← wb_rty_o
← wb_stall_o
← wb_int_o

3. Register description

3.1. Interrupt disable register

HW prefix: dma_eic_eic_idr
HW address: 0x8
C prefix: EIC_IDR
C offset: 0x20

Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - DMA_ERROR DMA_DONE
  • DMA_DONE [write-only]: DMA done interrupt
    write 1: disable interrupt 'DMA done interrupt'
    write 0: no effect
  • DMA_ERROR [write-only]: DMA error interrupt
    write 1: disable interrupt 'DMA error interrupt'
    write 0: no effect

3.2. Interrupt enable register

HW prefix: dma_eic_eic_ier
HW address: 0x9
C prefix: EIC_IER
C offset: 0x24

Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - DMA_ERROR DMA_DONE
  • DMA_DONE [write-only]: DMA done interrupt
    write 1: enable interrupt 'DMA done interrupt'
    write 0: no effect
  • DMA_ERROR [write-only]: DMA error interrupt
    write 1: enable interrupt 'DMA error interrupt'
    write 0: no effect

3.3. Interrupt mask register

HW prefix: dma_eic_eic_imr
HW address: 0xa
C prefix: EIC_IMR
C offset: 0x28

Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - DMA_ERROR DMA_DONE
  • DMA_DONE [read-only]: DMA done interrupt
    read 1: interrupt 'DMA done interrupt' is enabled
    read 0: interrupt 'DMA done interrupt' is disabled
  • DMA_ERROR [read-only]: DMA error interrupt
    read 1: interrupt 'DMA error interrupt' is enabled
    read 0: interrupt 'DMA error interrupt' is disabled

3.4. Interrupt status register

HW prefix: dma_eic_eic_isr
HW address: 0xb
C prefix: EIC_ISR
C offset: 0x2c

Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - DMA_ERROR DMA_DONE
  • DMA_DONE [read/write]: DMA done interrupt
    read 1: interrupt 'DMA done interrupt' is pending
    read 0: interrupt not pending
    write 1: clear interrupt 'DMA done interrupt'
    write 0: no effect
  • DMA_ERROR [read/write]: DMA error interrupt
    read 1: interrupt 'DMA error interrupt' is pending
    read 0: interrupt not pending
    write 1: clear interrupt 'DMA error interrupt'
    write 0: no effect

5. Interrupts

5.1. DMA done interrupt

HW prefix: dma_eic_dma_done
C prefix: DMA_DONE
Trigger: rising edge

DMA done interrupt line (rising edge sensitive).

5.2. DMA error interrupt

HW prefix: dma_eic_dma_error
C prefix: DMA_ERROR
Trigger: rising edge

DMA error interrupt line (rising edge sensitive).