SVEC FMC-TDC-1NS-5CHA

The memory map is divided in two parts: the Carrier (SVEC) part common to all SVEC designs, and two memory regions for TDCs (TDC1 and TDC2) part specific to the FMC-TDC-1NS-5CHA mezzanine.

svec_ref_fmc_tdc_mmap

svec_ref_fmc_tdc_mmap

SVEC FMC-TDC-1NS-5CHA memory map

1. Memory map summary

HW address Type Name HDL prefix C prefix
0x00000-0x0ffff SUBMAP svec-base-regs svec-base-regs svec-base-regs
0x10000-0x1ffff SUBMAP tdc1-base-regs tdc1-base-regs tdc1-base-regs
0x20000-0x2ffff SUBMAP tdc2-base-regs tdc2-base-regs tdc2-base-regs

2. Register description

SVEC base registers

svec_base_regs

svec_base_regs

SVEC base registers

1. Memory map summary

HW address Type Name HDL prefix C prefix
0x0000-0x003f SUBMAP metadata metadata metadata
0x0040-0x005f BLOCK csr csr csr
0x0040 REG csr.app_offset csr_app_offset csr.app_offset
0x0044 REG csr.resets csr_resets csr.resets
0x0048 REG csr.fmc_presence csr_fmc_presence csr.fmc_presence
0x004c REG csr.unused0 csr_unused0 csr.unused0
0x0050 REG csr.ddr_status csr_ddr_status csr.ddr_status
0x0054 REG csr.pcb_rev csr_pcb_rev csr.pcb_rev
0x0058 REG csr.ddr4_addr csr_ddr4_addr csr.ddr4_addr
0x005c REG csr.ddr5_addr csr_ddr5_addr csr.ddr5_addr
0x0080-0x008f SUBMAP therm_id therm_id therm_id
0x00a0-0x00bf SUBMAP fmc_i2c fmc_i2c fmc_i2c
0x00c0-0x00df SUBMAP flash_spi flash_spi flash_spi
0x0100-0x01ff SUBMAP vic vic vic
0x0200-0x02ff SUBMAP buildinfo buildinfo buildinfo
0x1000-0x17ff SUBMAP wrc_regs wrc_regs wrc_regs
0x2000-0x2fff SUBMAP ddr4_data ddr4_data ddr4_data
0x3000-0x3fff SUBMAP ddr5_data ddr5_data ddr5_data

2. Register description

2.1. csr.app_offset

HW prefix:csr_app_offset
HW address:0x40
C prefix:csr.app_offset
C block offset:0x0

offset to the application metadata

31 30 29 28 27 26 25 24
app_offset[31:24]
23 22 21 20 19 18 17 16
app_offset[23:16]
15 14 13 12 11 10 9 8
app_offset[15:8]
7 6 5 4 3 2 1 0
app_offset[7:0]
  • app_offset [ro]: offset to the application metadata

2.2. csr.resets

HW prefix:csr_resets
HW address:0x44
C prefix:csr.resets
C block offset:0x4

global and application resets

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - appl global
  • global [rw]: global and application resets
  • appl [rw]: global and application resets

2.3. csr.fmc_presence

HW prefix:csr_fmc_presence
HW address:0x48
C prefix:csr.fmc_presence
C block offset:0x8

presence lines for the fmcs

31 30 29 28 27 26 25 24
fmc_presence[31:24]
23 22 21 20 19 18 17 16
fmc_presence[23:16]
15 14 13 12 11 10 9 8
fmc_presence[15:8]
7 6 5 4 3 2 1 0
fmc_presence[7:0]
  • fmc_presence [ro]: presence lines for the fmcs

2.4. csr.unused0

HW prefix:csr_unused0
HW address:0x4c
C prefix:csr.unused0
C block offset:0xc

unused (status of gennum)

31 30 29 28 27 26 25 24
unused0[31:24]
23 22 21 20 19 18 17 16
unused0[23:16]
15 14 13 12 11 10 9 8
unused0[15:8]
7 6 5 4 3 2 1 0
unused0[7:0]
  • unused0 [ro]: unused (status of gennum)

2.5. csr.ddr_status

HW prefix:csr_ddr_status
HW address:0x50
C prefix:csr.ddr_status
C block offset:0x10

status of the ddr controllers

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - ddr5_calib_done ddr4_calib_done
  • ddr4_calib_done [ro]: Set when ddr4 calibration is done.
  • ddr5_calib_done [ro]: Set when ddr5 calibration is done.

2.6. csr.pcb_rev

HW prefix:csr_pcb_rev
HW address:0x54
C prefix:csr.pcb_rev
C block offset:0x14

pcb revision

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - rev[4:0]
  • rev [ro]: pcb revision

2.7. csr.ddr4_addr

HW prefix:csr_ddr4_addr
HW address:0x58
C prefix:csr.ddr4_addr
C block offset:0x18

address of data to read or to write

31 30 29 28 27 26 25 24
ddr4_addr[31:24]
23 22 21 20 19 18 17 16
ddr4_addr[23:16]
15 14 13 12 11 10 9 8
ddr4_addr[15:8]
7 6 5 4 3 2 1 0
ddr4_addr[7:0]
  • ddr4_addr [rw]: address of data to read or to write

2.8. csr.ddr5_addr

HW prefix:csr_ddr5_addr
HW address:0x5c
C prefix:csr.ddr5_addr
C block offset:0x1c

address of data to read or to write

31 30 29 28 27 26 25 24
ddr5_addr[31:24]
23 22 21 20 19 18 17 16
ddr5_addr[23:16]
15 14 13 12 11 10 9 8
ddr5_addr[15:8]
7 6 5 4 3 2 1 0
ddr5_addr[7:0]
  • ddr5_addr [rw]: address of data to read or to write

First FMC-TDC-1NS-5CHA

See TDC memory map.

Second FMC-TDC-1NS-5CHA

See TDC memory map.